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1 fujitsu semiconductor data sheet ds04?1353?e assp dual serial input pll frequency synthesizer MB15F02L n description the fujitsu MB15F02L is a serial input phase locked loop (pll) frequency synthesizer with a 1.2 ghz and a 250 mhz prescalers. a 64/65 or a 128/129 for the 1.2 ghz prescaler, and a 16/17 or a 32/33 for 250 mhz prescaler can be selected that enables pulse swallow operation. the latest bicmos process technology is used, resuitantly a supply current is limited as low as 4.0 ma typ. at a supply voltage of 3.0 v. furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. as a result of this, MB15F02L is ideally suitable for digital mobile communications, such as gsm (global system for mobile communications). n features high frequency operation rf synthesizer: 1.2 ghz max. / if synthesizer: 250 mhz max. low power supply voltage: v cc = 2.7 to 3.6 v very low power supply current : i cc = 4.0 ma typ. (v cc = 3 v) power saving function : supply current at power saving mode typ.0.1 m a (v cc = 3 v), max.10 m a (i ps1 = i ps2 ) dual modulus prescaler : 1.2 ghz prescaler (64/65,128/129) , 250 mhz prescaler (16/17,32/33) serial input 14-bit programmable reference divider: r = 5 to 16,383 serial input 18-bit programmable divider consisting of: - binary 7-bit swallow counter: 0 to 127 - binary 11-bit programmable counter: 5 to 2,047 on?hip high performance charge pump circuit and phase comparator, achieving high?peed lock?p and low phase noise on?hip phase control for phase comparator wide operating temperature: ta = ?0 to 85 c n packages 16-pin, plastic ssop (fpt-16p-m05) 16-pin, plastic bcc (lcc-16p-m03)
2 MB15F02L n pin assignments top 1 2 3 4 5 6 16 15 14 13 12 11 7 8 10 9 view gnd rf gnd if ? if oscin vcc if ps if do if ld/fout clock data le ? rf vcc rf x? rf ps rf do rf to p view gnd if ? if oscin vcc if date le ? rf v ccrf ps if x? rf ps rf ld/fout (lcc-16p-m03) gnd rf clock 1 2 3 4 5 6 78 9 10 11 12 13 14 16 15 bcc-16 pin (fpt-16p-m05) ssop-16 pin do if do rf
3 MB15F02L n pin descriptions pin no. pin name i/o descriptions ssop bcc 1 16 gnd rf ground for rf-pll section. 2 1 oscin i the programmable reference divider input. tcxo should be connected with a ac coupling capacitor. 3 2 gnd if ground for the if-pll section. 4 3 fin if i prescaler input pin for the if-pll. the connection with vco should be ac coupling. 54 v ccif power supply voltage input pin for the if-pll section. 6 5 ld/fout o lock detect signal output (ld) / phase comparator monitoring output (fout) the output signal is selected by a lds bit in a serial data. lds bit = ? ; outputs fout signal lds bit = ? ; outputs ld signal 76 ps if i power saving mode control for the if-pll section. this pin must be set at ? power-on. (open is prohibited.) ps if = ??; normal mode ps if = ??; power saving mode 87 d oif o charge pump output for the if-pll section. phase characteristics of the phase detector can be reversed by fc-bit. 98 do rf o charge pump output for the rf-pll section. phase characteristics of the phase detector can be reversed by fc-bit. 10 9 ps rf i power saving mode control for the rf-pll section. this pin must be set at ? power-on. (open is prohibited.) ps rf = ? ; normal mode ps rf = ? ; power saving mode 11 10 xfin rf i prescaler complimentary input for the rf-pll section. this pin should be grounded via a capacitor. 12 11 v ccrf power supply voltage input pin for the rf-pll section, the shift register and the oscillator input buffer. when power is off, latched data of rf-pll is cancelled. 13 12 fin rf i prescaler input pin for the rf-pll. the connection with vco should be ac coupling. 14 13 le i load enable signal input (with the schmitt trigger circuit.) when le is ?? data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. 15 14 data i serial data input (with the schmitt trigger circuit.) a data is transferred to the corresponding latch (if-ref counter, if-prog. counter, rf-ref. counter, rf-prog. counter) according to the control bit in a serial data. 16 15 clock i clock input for the 23-bit shift register (with the schmitt trigger circuit.) one bit data is shifted into the shift register on a rising edge of the clock.
4 MB15F02L n block diagram ps rf 2 4 14 schmitt circuit 15 schmitt circuit 16 schmitt circuit c n 1 23-bit shift register latch selector 1 v ccrf 12 gnd rf ? if oscin le data clock 5 v ccif prescaler (if?ll) 16/17,32/33 intermittent mode control (if?ll) c n 2 3-bit latch lds sw if fc if binary 7-bit swallow counter (if?ll) binary 11-bit programmable counter(if?ll) phase comp. (if?ll) charge pump (if?ll) super charger 7 ps if 7-bit latch 11-bit latch 2-bit latch 14-bit latch binary 14?it pro- grammable ref. counter (if?ll) 10 13 ? rf prescaler (rf?ll) 64/65, 128/129 3-bit latch lds sw rf fc rf binary 7-bit swallow counter (rf?ll) binary 11-bit programmable counter (rf?ll) charge pump (rf?ll) super charger 7-bit latch 11-bit latch t1 t2 2-bit latch 14-bit latch binary 14-bit pro- grammable ref. counter (rf?ll) t1 t2 or lock det. (if?ll) lock det. selector ld fr if fr rf fp if fp rf 9 do rf 8 do if and 6 ld/fout 11 x? rf 3 gnd if fr if fr rf ld if fp rf fp if intermittent mode control (rf?ll) phase comp. (rf?ll) ld rf note : ssop-16 pin
5 MB15F02L n absolute maximum ratings (see warning) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. handling precautions this device should be transported and stored in anti-static containers. this is a static-sensitive device; take proper anti-esd precautions. ensure that personnel and equipment are properly grounded. cover workbenches with grounded conductive mats. always turn the power supply off before inserting or removing the device from its socket. protect leads with a conductive sheet when handling or transporting pc boards with devices. parameter symbol rating unit remark min. max. power supply voltage v cc ?.5 +4.0 v input voltage v i ?.5 v cc +0.5 v output voltage v o ?.5 v cc +0.5 v output current i o ?0 +10 ma except do output i do ?5 +25 ma do output storage temperature t stg ?5 +125 c parameter symbol value unit remark min. typ. max. power supply voltage v cc 2.7 3.0 3.6 v input voltage v i gnd v cc v operating temperature ta ?0 +85 c
6 MB15F02L n electrical characteristics (v cc = 2.7 to 3.6 v, ta = ?0 to +85 c) *1: conditions ; v ccif = 3 v, ta = 25 c, in locking state. *2: conditions ; v ccrf = 3 v, ta = 25 c, in locking state. *3: fosc = 12.8 mhz , v cc = 3.0 v, ta = 25 c *4: ac coupling with a 1000 pf capacitor connected. *5: the symbol (minus) means direction of current ?w. parameter symbol condition value unit min. typ. max. power supply current i ccif *1 ? if = 250 mhz, fosc = 12 mhz 1.5 ma i ccrf *2 ? rf = 1200 mhz, fosc = 12 mhz 2.5 power saving current ips if v ccif current at ps if = ? 0.1 *3 10 m a i ps rf v ccrf current at ps if/rf = ? 0.1 *3 10 operating frequency ? if *4 fin if if-pll 50 250 mhz ? rf *4 fin rf rf-pll 100 1200 oscin f osc ?40 input sensitivity ? if vfin if if-pll, 50 w termination ?0 +2 dbm ? rf vfin rf rf-pll, 50 w termination ?0 +2 dbm oscin v osc 0.5 v cc vp-p input voltage data, clock, le v ih schmitt trigger input v cc 0.7 + 0.4 v v il schmitt trigger input v cc 0.3 ?0.4 ps if , ps rf v ih ? cc 0.7 v v il v cc 0.3 input current data, clock, le, ps if , ps rf i ih *5 ?.0 +1.0 m a i il *5 ?.0 +1.0 oscin i ih 0 +100 m a i il *5 ?00 0 output voltage ld/fout v oh v cc = 3.0 v, i oh = ?.0 ma v cc ?0.4 v v ol v cc = 3.0 v, i ol = 1.0 ma 0.4 do if , do rf v doh v cc = 3.0 v, i doh = ?.0 ma v cc ?0.4 v v dol v cc = 3.0 v, i dol = 1.0 ma 0.4 high impedance cutoff current do if , do rf i off v cc = 3.0 v, v off = gnd to v cc 3.0 na output current ld/fout i oh *5 v cc = 3.0 v ?.0 ma i ol v cc = 3.0 v 1.0 do if , do rf i doh *5 v cc = 3.0 v, v doh = 2.0 v, ta = 25 c ?1 6 ma i dol v cc = 3.0 v, v dol = 1.0 v, ta = 25 c 815
7 MB15F02L n functional descriptions 1. pulse swallow function the divide ratio can be calculated using the following equation: f vco = {(m n) + a} f osc ? r (a < n) f vco : output frequency of external voltage controlled oscillator (vco) m: preset divide ratio of dual modulus prescaler (16 or 32 for if-pll, 64 or 128 for rf-pll) n: preset divide ratio of binary 11-bit programmable counter (5 to 2,047) a: preset divide ratio of binary 7-bit swallow counter (0 a 127) f osc : reference oscillation frequency r: preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383) 2. serial data input serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of if/rf-pll sections, programmable reference dividers of if/rf pll sections are controlled individually. serial data of binary data is entered through data pin. on rising edge of clock, one bit of serial data is transferred into the shift register. when load enable signal is high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. table1. control bit (1) shift register con?uration control bit destination of serial data cn1 cn2 l l the programmable reference counter for the if-pll. h l the programmable reference counter for the rf-pll. l h the programmable counter and the swallow counter for the if-pll h h the programmable counter and the swallow counter for the rf-pll programmable reference counter cnt1, 2 : control bit [table. 1] r1 to r14 : divide ratio setting bits for the programmable reference counter (5 to 16,383) [table. 2] t1, 2 : test purpose bit [tabl e.3] x : dummy bits(set ? or ?? note: data input with msb ?st. c n 1 1 2 t 1 3 r 1 4 r 2 5 r 3 6 r 4 7 r 5 8 r 6 9 r 7 10 r 8 11 r 9 12 r 10 13 r 11 14 r 12 15 r 13 16 r 14 17 lsb msb data flow c n 2 t 2 18 x x 19 x 20 x 21 x 22 23
8 MB15F02L (2) data setting table2. binary 14-bit programmable reference counter data setting note: divide ratio less than 5 is prohibited. table3. test purpose bit setting divide ratio (r) r 14 r 13 r 12 r 11 r 10 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 5 00000000000101 6 00000000000110 16383 11111111111111 t 1 t 2 ld/fout pin state l l outputs fr if. h l outputs fr rf. l h outputs fp if. h h outputs fp rf. programmable counter cnt1, 2 : control bit [table. 1] n1 to n11 : divide ratio setting bits for the programmable counter (5 to 2,047) [table. 4] a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) [table. 5] sw if/rf : divide ratio setting bit for the prescaler [table. 6] (16/17 or 32/33 for the if-pll, 64/65 or 128/129 for the rf-pll) fc if/rf : phase control bit for the phase detector [table. 7] lds : ld/fout signal select bit [table. 8] note: data input with msb ?st. c n 1 1 2 l d 3 f c 4 a 1 5 a 2 6 a 3 7 a 4 8 a 5 9 a 6 10 a 7 11 n 1 12 n 2 13 n 3 14 n 4 15 n 5 16 n 6 17 lsb msb data flow c n 2 s w 18 n 7 n 8 19 n 9 20 n 10 21 n 11 22 23 s if/ rf if/ rf
9 MB15F02L table4. binary 11-bit programmable counter data setting note: divide ratio less than 5 is prohibited. table5. binary 7-bit swallow counter data setting note: divide ratio (a) range = 0 to 127 table6. prescaler data setting table7. phase comparator phase switching data setting note: z = high-impedance depending upon the vco and lpf polarity, fc bit should be set. table8. ld/fout output select data setting divide ratio (n) n 11 n 10 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 5 00000000101 6 00000000110 2047 11111111111 divide ratio (a) a 7 a 6 a 5 a 4 a 3 a 2 a 1 0 0000000 1 0000001 127 1111111 sw = ? sw = ? prescaler divide ratio if-pll 16/17 32/33 rf-pll 64/65 128/129 fc if,rf = h fc if,rf = l do if,rf fr > fp h l fr = fp z z fr < fp l h vco polarity (1) (2) lds ld/fout output signal h fout (fr if/rf , fp if/rf ) signals l ld signal vco output voltage vco output frequency (1) (2)
10 MB15F02L 3. power saving mode (intermittent mode control circuit) setting a ps if(rf) pin to low, if-pll (rf-pll) enters into power saving mode resultant current consumption can be limited to 10 m a (typ.). setting ps pin to high, power saving mode is released so that the device works normally. in addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode. in general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. such case, if the pll is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an unde?ed phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. to prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up. thus keeping the loop locked. ps pin must be set ? at power-on. allow 1 m s after frequency stabilization on power-up for exiting the power saving mode (ps: l to h) serial data can be entered during the power saving mode. during the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10 m a per one pll section. at that time, the do and ld become the same state as when a loop is locking. that is, the do becomes high impedance. a vco control voltage is naturally kept at the locking voltage which de?ed by a lpfs time constant. as a result of this, vcos frequency is kept at the locking frequency. ps if ps rf if-pll counters rf-pll counters osc input buffer l l off off off h l on off on l h off on on h h on on on v cc on clock data le ps (1) (2) (3) (1) ps = l (power saving mode) at power-on (2)set serial data after power supply remains stable. (3)release saving mode(ps : l ? h) after setting serial data.
11 MB15F02L 4. serial data input timing 2nd. data 1st. data invalid data control bit lsb msb clock data le t 7 t 1 t 2 t 5 t 3 t 6 t 4 on rising edge of the clock, one bit of the data is transferred into the shift register. parameter unit max. typ. min. t1 t2 t3 t4 ns ns ns ns 20 20 30 20 30 100 100 t5 t6 t7 ns ns ns parameter unit max. typ. min.
12 MB15F02L n phase detector output waveform note: phase error detection range = - 2 p to +2 p pulses on do if/rf signals are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on oscin input frequency as follows. t wu 3 4/fosc: i.e. t wu 3 312.5 ns when foscin = 12.8 mhz t wl 8/fosc: i.e. t wl 625.0 ns when foscin = 12.8 mhz t wu fr if/rf fp if/rf t wl ld (fc bit = high) do if/rf z l (fc bit = low) z h do if/rf if-pll section rf-pll section ld output locking state / power saving state locking state / power saving state locking state / power saving state h l l l unlocking state unlocking state unlocking state locking state / power saving state unlocking state ld output logic table
13 MB15F02L n test circuit (?, osc in input sensitivity test) MB15F02L 50 w 1 2 5 4 v ccif 0.1 m f 16 15 14 12 13 11 50 w 1000 pf 1000 pf s.g 0.1 m f v ccrf fout oscilloscope gnd 7 3 10 6 s.g 50 w 1000 pf 8 9 1000 pf controller (divide ratio setting) s.g note : ssop-16 pin
14 MB15F02L n typical characteristics 1. ? input sensitivity 2. oscin input sensitivity 10 5 0 ? ?0 ?5 ?0 ?5 ?0 input sensitivity of f in (rf) vs. input frequency 0 vfin rf (dbm) fin rf (mhz) 500 1000 1500 2000 ta = +25 c v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ?5 ?0 spec 10 5 0 ? ?0 ?5 ?0 ?5 ?0 input sensitivity of f in (if) vs. input frequency 0 vfin if (dbm) fin if (mhz) 250 500 750 1000 ta = +25 c v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ?5 ?0 spec +10 ?0 ?0 ?0 ?0 0 input sensitivity of oscin vs. input frequency input frequency f osc 0 50 100 (mhz) input sensitivity v osc ta = +25 c v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec
15 MB15F02L 3. d orf output current 0.0 0.0 i doh vs. v doh v doh (v) i doh (ma) ?5.0 5.000 v cc = 3.0 v ta = +25 c i dol vs. v dol v dol (v) i dol (ma) .0000 25.00 5.000 v cc = 3.0 v ta = +25 c .0000
16 MB15F02L 4. d oif output current i dol vs. v dol v dol (v) i dol (ma) .0000 .0000 25.00 5.000 v cc = 3.0 v ta = +25 c .0000 .0000 i doh vs. v doh v doh (v) i doh (ma) ?5.00 5.000 v cc = 3.0 v ta = +25 c
17 MB15F02L 5. ? input impedance 309 w ?40.13 w 100 mhz 29.773 w ?86.98 w 400 mhz 12.648 w ?3.883 w 800 mhz 1 : 2 : 3 : fin fin rf 3 start 100.000 000 mhz stop 1 200.000 000 mhz 4 : 10.252 w ?3.703 w 1.2 ghz 1 2 4 791.22 w ?07.56 w 50 mhz 89.189 w ?78.02 w 200 mhz 58.797 w ?04.36 w 250 mhz 1 : 2 : 3 : fin fin if start 50.000 000 mhz stop 500.000 000 mhz
18 MB15F02L 6. osc in input impedance 7.138 k w ?3.837 k w 3 mhz 257 w ?.214 k w 10 mhz 154 w ?.9594 k w 20 mhz 83.88 w ?.5472 k w 40 mhz 1 : 2 : 3 : 4 : osc in osc in start 1.000 000 mhz stop 50.000 000 mhz 4 3 2 1
19 MB15F02L n reference information (lock up time, phase noise, reference leakage) s.g oscin fin do spectrum analyzer lpf vco test circuit f vco = 810.45 mhz k v = 17 mhz/v fr = 25 khz f osc = 14.4 mhz 9.1 k w 2.7 k w 0.068 m f 1500 pf 6800 pf lpf ?.0 dbm 10 db/ d mkr ?4.00 db 25.0 khz rl 74.0 dbc span 200.0 khz center 810.4500 mhz * swp 1.00 sec * vbw 1.0 khz * rbw 1.0 khz pll reference leakage ?.0 dbm 10 db/ d mkr ?1.83 db 1.67 khz rl c/n ~ 71.8 dbc/hz span 20.00 khz center 810.45000 mhz * swp 3.00 sec * vbw 100 hz * rbw 100 hz bw ~ 4.17 khz pll phase noise 30.00500 mhz 2.000 khz/diu 29.99500 mhz 0 s 8.0000000 ms 50.00000 mhz 10.00000 mhz/diu 0 hz 0 s 8.0000000 ms 810.45 mhz ? 826.45 mhz 1 khz 1.32 ms pll lock up time 30.00500 mhz 2.00 khz/diu 29.99500 mhz 0 s 8.0000000 ms 50.00000 mhz 5.00000 mhz/diu 25.00000 mhz 0 s 8.0000000 ms 826.45 mhz ? 810.45 mhz 1.64 ms pll lock up time
20 MB15F02L n application example vco lpf tcxo 3 v 1000 pf 0.1 m f output 1000 pf from controller data ? rf 16 15 14 13 12 11 10 9 123456 7 8 v ccrf clock le x? rf ps rf do rf 3 v 0.1 m f 1000 pf 1000 pf vco lpf output lock det. osc in ? if v ccif gnd rf gnd if ld/fout ps if do if MB15F02L note : ssop-16 pin
21 MB15F02L n ordering information part number package remarks MB15F02Lpfv1 16 pin, plastic ssop (fpt-16p-m05) MB15F02Lpv 16 pin, plastic bcc (lcc-16p-m03)
22 MB15F02L n package dimensions (continued) *: these dimensions do not include resin protrusion. +0.20 C0.10 +.008 C.004 +0.10 C0.05 +.004 C.002 +0.05 C0.02 +.002 C.001 index "a" 0.10(.004) 1.25 .049 0.22 .009 0.15 .006 (.0256.0047) * (.173.004) (.252.008) nom 6.400.20 4.400.10 5.40(.213) 0.650.12 * 5.000.10(.197.004) 4.55(.179)ref details of "a" part 0 10 (stand off) 0.100.10(.004.004) (.020.008) 0.500.20 1994 fujitsu limited f16013s-2c-4 c dimensions in mm (inches). 16 pins, plastic ssop (fpt-16p-m05)
23 MB15F02L (continued) c 1996 fujitsu limited c16014s-1c-1 0.3250.10 (.013.004) 0.65(.026)typ 3.40(.134)typ "a" 0.400.10 (.016.004) 3.25(.128) 0.80(.032) typ typ 4.200.10 (.165.004) 4.550.10 (.179.004) 0.80(.032)max 0.0850.040 (.003.002) (stand off) 0.40(.016) 45? e-mark 0.05(.002) 6 9 1 14 9 14 1 6 0.400.10 (.016.004) 0.750.10 (.030.004) details of "a" part 1.55(.061)typ 1.725(.068) typ "b" 0.600.10 (.024.004) 0.600.10 (.024.004) details of "b" part dimensions in mm (inches). (mounting height) 16 pins, plastic bcc (lcc-16p-m03)
24 MB15F02L fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9706 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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